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E28F200CVT80 参数 Datasheet PDF下载

E28F200CVT80图片预览
型号: E28F200CVT80
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位SmartVoltage引导块闪存系列 [2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY]
分类和应用: 闪存
文件页数/大小: 55 页 / 633 K
品牌: INTEL [ INTEL ]
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2-MBIT SmartVoltage BOOT BLOCK FAMILY  
4.9.1 APPLYING VCC VOLTAGES  
E
required. If VCC ramps faster than 1V/100 µs (0.01  
V/µs), then a delay of 2 µs is required before  
When applying VCC voltage to the device, a delay  
may be required before initiating device operation,  
depending on the VCC ramp rate. If VCC ramps  
slower than 1V/100 µs (0.01 V/µs) then no delay is  
initiating device operation. RP#  
=
GND is  
recommended during power-up to protect against  
spurious write signals when VCC is between VLKO  
and VCCMIN  
.
VCC Ramp Rate  
Required Timing  
1V/100 µs  
> 1V/100 µs  
No delay required.  
A delay time of 2 µs is required before any device operation is initiated, including read  
operations, command writes, program operations, and erase operations. This delay is  
measured beginning from the time VCC reaches VCCMIN ( 3.0 V for 3.3 ± 0.3 V operation;  
and 4.5 V for 5 V operation).  
NOTES:  
1. These requirements must be strictly followed to guarantee all other read and write specifications.  
2. To switch between 3.3 V and 5 V operation, the system should first transition VCC from the existing voltage range to GND,  
and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations  
pending or in progress.  
3. These guidelines must be followed for any VCC transition from GND.  
4.10 Capacitance  
TA = 25 °C, f = 1 MHz  
Symbol  
CIN  
Parameter  
Note  
Typ  
6
Max  
8
Unit  
pF  
Conditions  
VIN = 0V  
VOUT = 0V  
Input Capacitance  
Output Capacitance  
1
1
COUT  
10  
12  
pF  
NOTE:  
1. Sampled, not 100% tested.  
44  
SEE NEW DESIGN RECOMMENDATIONS  
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