2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all
product versions (packages and speeds).
2.
3. Block erases and word/byte programs inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and
VPPLK
I
CCES is specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR
.
.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH
7. For the 28F002B address pin A10 follows the COUT capacitance numbers.
8. For all BV/CV parts, VLKO = 2.0 V for 3.3 V and 5.0 V operations.
.
3.0
OUTPUT
INPUT
1.5
TEST POINTS
1.5
0.0
0530_12
NOTE:
AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 19. 3.3 V Input Range and Measurement Points
2.4
2.0
0.8
2.0
0.8
INPUT
OUTPUT
TEST POINTS
0.45
0530_13
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
)
Figure 20. 5 V Input Range and Measurement Points
VCC
Test Configuration Component Values
Test Configuration
3.3 V Standard Test
5 V Standard Test
CL (pF) R1 (Ω) R2 (Ω)
R
R
50
990
580
770
390
1
100
DEVICE
UNDER
TEST
NOTE: CL includes jig capacitance.
OUT
C
L
2
0530_14
NOTE: See table for component values.
Figure 21. Test Configuration
48
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
