E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
3.0
OUTPUT
INPUT
1.5
TEST POINTS
1.5
0.0
NOTE:
AC test inputs are driven at 3.0 V for a logic “1” and 0.0 V for a logic “0.” Input timing begins, and output timing ends, at 1.5 V.
Input rise and fall times (10% to 90%) <10 ns.
0530_12
Figure 12. 3.3 V Inputs and Measurement Points
2.4
2.0
2.0
0.8
INPUT
OUTPUT
TEST POINTS
0.8
0.45
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL
and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
)
0530_13
Figure 13. 5 V Inputs and Measurement Points
Test Configuration Component Values
VCC
Test Configuration
CL (pF) R1 (Ω) R2 (Ω)
R
R
3.3 V Standard Test
5 V Standard Test
5 V High-Speed Test
50
100
30
990
580
580
770
390
390
1
DEVICE
UNDER
TEST
OUT
NOTE: CL includes jig capacitance.
C
L
2
0530_14
NOTE: See table for component values.
Figure 14. Test Configuration
33
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
