E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
4.2.1
APPLYING V
VOLTAGES
CC
required. If VCC ramps faster than 1V/100 µs (0.01
V/µs), then a delay of 2 µs is required before
When applying VCC voltage to the device, a delay
may be required before initiating device operation,
depending on the VCC ramp rate. If VCC ramps
slower than 1V/100 µs (0.01 V/µs) then no delay is
initiating device operation. RP#
=
GND is
recommended during power-up to protect against
spurious write signals when VCC is between VLKO
and VCCMIN
.
VCC Ramp Rate
Required Timing
≤ 1V/100 µs
> 1V/100 µs
No delay required.
A delay time of 2 µs is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay is
measured beginning from the time VCC reaches VCCMIN (3.0 V for 3.3 ± 0.3 V operation;
and 4.5 V for 5 V operation).
NOTES:
1. These requirements must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3 V and 5 V operation, the system should first transition VCC from the existing voltage range to GND,
and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations
pending or in progress.
3. These guidelines must be followed for any VCC transition from GND.
4.3
Capacitance
TA = 25 °C, f = 1 MHz
Symbol
CIN
Parameter
Note
1
Typ
6
Max
8
Unit
pF
Conditions
VIN = 0 V
VOUT = 0 V
Input Capacitance
Output Capacitance
COUT
1, 2
10
12
pF
NOTES:
1. Sampled, not 100% tested.
2. For the 28F002B, address pin A10 follows the COUT capacitance numbers.
29
SEE NEW DESIGN RECOMMENDATIONS
INTEL [ INTEL ]
