SMART 5 BOOT BLOCK MEMORY FAMILY
3.3 Boot Block Locking
E
functionality is required, and 12 V is not available
in-system, please consider using the 48-TSOP
package, which has
a
WP# pin and can be
The boot block family architecture features
a
unlocked with a logic-level signal. All other density-
package combinations have WP# pins.
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks.
Table 8. Write Protection Truth Table
VPP
RP# WP#
Write Protection
Provided
VIL
X
X
X
All Blocks Locked
3.3.1
V
PP = VIL FOR COMPLETE
PROTECTION
≥ VPPLK
VIL
All Blocks Locked
(Reset)
For complete write protection of all blocks in the
device, the VPP voltage can be held low. When VPP
is below VPPLK, any program or erase operation will
result in a error in the status register.
≥ VPPLK VHH
X
All Blocks Unlocked
≥ VPPLK
≥ VPPLK
VIH
VIH
VIL Boot Block Locked
VIH All Blocks Unlocked
3.3.2
WP# = VIL FOR BOOT BLOCK
LOCKING
4.0 DESIGN CONSIDERATIONS
When WP# = VIL, the boot block is locked and any
program or erase operation to the boot block will
result in an error in the status register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
The following section discusses recommended
design considerations which can improve the
robustness of system designs using flash memory.
when RP# = VHH
.
4.1
Power Consumption
3.3.3
RP# = VHH OR WP# = VIH FOR BOOT
BLOCK UNLOCKING
Intel flash components contain features designed to
reduce power requirements. The following sections
will detail how to take advantage of these features.
Two methods can be used to unlock the boot block:
1. WP# = VIH
4.1.1
ACTIVE POWER
2. RP# = VHH
Asserting CE# to a logic-low level and RP# to a
logic-high level places the device in the active
mode. Refer to the DC Characteristics table for ICCR
current values.
If both or either of these two conditions are met, the
boot block will be unlocked and can be
programmed or erased.
The Write Proctection Truth Table, Table 8, clearly
defines the write protection methods.
4.1.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) provides low-
power operation in active mode. Power Reduction
Control (PRC) circuitry allows the device to put
itself into a low current state when not being
accessed. After data is read from the memory
array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical ICC current is less than 1 mA. The device
stays in this static state with outputs valid until a
new location is read.
3.3.4
NOTE FOR 8-MBIT 44-PSOP
PACKAGE
The 8-Mbit in the 44-PSOP package does not have
a WP# because no other pins were available for the
8-Mbit upgrade address. Thus, in this density-
package combination only, VHH (12 V) on RP# is
required to unlock the boot block and unlocking with
a logic-level signal is not possible. If this unlocking
24
ADVANCE INFORMATION
INTEL [ INTEL ]
