SMART 5 BOOT BLOCK MEMORY FAMILY
E
3.2.2
READ IDENTIFIER
3.2
Modes of Operation
To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the intelligent identifier command (90H) or
by taking the A9 pin to VID. Once in intelligent
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. An additional mode,
erase suspend to read, is available only during
block erasures. These modes are reached using
identifier read mode, A0
=
0
outputs the
manufacturer’s identification code and A0
=
1
the commands summarized in Table 5.
A
outputs the device code. In byte-wide mode, only
the lower byte of the above signatures is read
(DQ15/A–1 is a “don’t care” in this mode). See
Table 4 for product signatures. To return to read
array mode, write a Read Array command (FFH).
comprehensive chart showing the state transitions
is in Appendix A.
3.2.1
READ ARRAY
After initial device power-up or return from deep
power-down mode, the device defaults to read
array mode. This mode can also be entered by
writing the Read Array command (FFH). The device
remains in this mode until another command is
written.
3.2.3
READ STATUS REGISTER
The status register indicates when a program or
erase operation is complete, and the success or
failure of that operation. The status register is
output when the device is read in read status
register mode, which can be entered by issuing the
Read Status (70H) command to the CUI. This mode
is automatically entered when a program or erase
operation is initiated, and the device remains in this
mode after the operation has completed. Status
register bit codes are defined in Table 7.
Data is read by presenting the address of the read
location in conjunction with a read bus operation.
Once the WSM has started a program or block
erase operation, the device will not recognize the
Read Array command until the WSM completes its
operation unless the WSM is suspended via an
Erase Suspend command. The Read Array
command functions independently of the VPP
The status register bits are output on DQ0–DQ7, in
both byte-wide (x8) or word-wide (x16) mode. In the
word-wide mode, the upper byte, DQ8–DQ15
outputs 00H during a Read Status command. In the
byte-wide mode, DQ8–DQ14 are tri-stated and
DQ15/A–1 retains the low order address function.
,
voltage and RP# can be VIH or VHH
.
During system design, consideration should be
taken to ensure address and control inputs meet
required input slew rates of <10 ns as defined in
Figures 11 and 12.
Note that the contents of the status register are
latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if
status register contents change while being read.
CE# or OE# must be toggled with each subsequent
status read, or the status register will not indicate
completion of a program or erase operation.
Table 4. Intelligent Identifier Codes
Product Mfr. ID
Device ID
-T
-B
Top Boot Bottom Boot
28F004
28F200
28F400
28F800
89H
78H
79H
Issue a Read Array (FFH) command to return to
read array.
0089 H
0089 H
0089 H
2274 H
4470 H
889C H
2275 H
4471 H
889D H
3.2.3.1
Clearing the Status Register
NOTE:
In byte-mode, the upper byte will be tri-stated.
Status register bits SR.5, SR.4, and SR.3 are set to
“1”s when appropriate by the WSM but can only be
reset by the Clear Status Register command.
These bits indicate various failure conditions (see
Table 7). By requiring system software to reset
16
ADVANCE INFORMATION
INTEL [ INTEL ]
