28F320J5 and 28F640J5
5.0
Design Considerations
5.1
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,
CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
• Lowest possible memory power dissipation.
• Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 2)
while OE# should be connected to all memory devices and the system’s READ# control line. This
assures that only selected memory devices have active outputs while de-selected memory devices
are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent
unintended writes during system power transitions. POWERGOOD should also toggle during
system reset.
5.2
STS and Block Erase, Program, and Lock-Bit Configuration
Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a
hardware method of detecting block erase, program, and lock-bit configuration completion. In
default mode, it transitions low after block erase, program, or lock-bit configuration commands and
returns to High Z when the WSM has finished executing the internal algorithm. For alternate
configurations of the STS pin, see the Configuration command.
STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the device is in block erase suspend (with programming
inactive) or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers
are interested in three supply current issues; standby current levels, active current levels and
transient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash
memory devices draw their power from three VCC pins (these devices do not include a VPP pin), it
is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic
capacitor between each of the device’s three VCC pins (this includes VCCQ) and ground. These
high-frequency, low-inductance capacitors should be placed as close as possible to package leads
on each Intel StrataFlash memory device. Each device should have a 0.1 µF ceramic capacitor
connected between its VCC and GND. These high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed between VCC and GND at the array’s power supply
connection. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductance.
38
Datasheet
INTEL [ INTEL ]
