28F320J5 and 28F640J5
Table 15. Write Protection Alternatives
Master
Lock-Bit
Block
Lock-Bit
Operation
RP#
or
Effect
V
IH
Block Erase or Program
0
1
Block Erase and Program Enabled
V
HH
X
V
Block is Locked. Block Erase and Program Disabled
IH
Block Lock-Bit Override. Block Erase and Program
Enabled
V
HH
V
V
or
HH
IH
Set or Clear Block Lock-Bits
0
1
X
X
Set or Clear Block Lock-Bit Enabled
Master Lock-Bit Is Set. Set or Clear Block Lock-Bit
Disabled
V
IH
Master Lock-Bit Override. Set or Clear Block Lock-Bit
Enabled
V
V
HH
Set Master Lock-Bit
X
X
V
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
IH
HH
Table 16. Configuration Coding Definitions
Pulse on
Program
Pulse on
Reserved
Bits 7—2
Erase
Complete(1)
Complete(1)
Bit 1
Bit 0
DQ –DQ = Reserved
DQ –DQ are reserved for future use.
7 2
7
2
DQ –DQ = STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Program complete
11 = pulse on Erase or Program Complete
default (DQ –DQ = 00) RY/BY#, level mode
1 0
1
0
— used to control HOLD to a memory controller to prevent
accessinga flash memory subsystem while any flash device's
WSM is busy.
configuration 01 ER INT, pulse mode
— used to generate a system interrupt pulse when any flash
device in an array has completed a Block Erase or sequence of
Configuration Codes 01b, 10b, and 11b are all pulse mode
such that the STS pin pulses low then high when the operation Queued Block Erases. Helpful for reformattingblocks after file
indicated by the given configuration is completed. system free space reclamation or “cleanup”
Configuration Command Sequences for STS pin configuration configuration 10 PR INT, pulse mode
(maskingbits DQ –DQ to 00h) are as follows:
— used to generate a system interrupt pulse when any flash
device in an array has complete a Program operation. Provides
highest performance for servicing continuous buffer write
operations.
7
2
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
configuration 11 ER/PR INT, pulse mode
— used to generate system interrupts to trigger servicing of
flash arrays when either erase or program operations are
completed when a common interrupt service routine is desired.
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of
250 ns.
30
Datasheet
INTEL [ INTEL ]
