28F320J5 and 28F640J5
4.8
Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number
of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the
Write to Buffer setup command is issued along with the Block Address (see Figure 6, “Write to
Buffer Flowchart” on page 32). At this point, the eXtended Status Register (XSR, see Table 17,
“Status Register Definition” on page 31) information is loaded and XSR.7 reverts to “buffer
available” status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring
XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1.
When XSR.7 transitions to a “1,” the buffer is ready for loading.
Now a word/byte count is given to the part with the Block Address. On the next write, a device
start address is given along with the write buffer data. Subsequent writes provide additional device
addresses and data, depending on the count. All subsequent addresses must lie within the start
address plus the count.
Internally, this device programs many flash cells in parallel. Because of this parallel programming,
maximum programming performance and lower power are obtained by aligning the start address at
the beginning of a write buffer boundary (i.e., A4–A0 of the start address = 0).
After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM
(Write State Machine) to begin copying the buffer data to the flash array. If a command other than
Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated
and status register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue
another Write to Buffer setup command and check XSR.7.
If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set
to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do
not successfully program to “0”s. If a program error is detected, the status register should be
cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an
erase), the device will not accept any more Write to Buffer commands. Additionally, if the user
attempts to program past an erase block boundary with a Write to Buffer command, the device will
abort the write to buffer operation. This will generate an “Invalid Command/Sequence” error and
status register bits SR.5 and SR.4 will be set to a “1.”
Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted
while VPEN ≤ VPENLK, status register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts
with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally,
successful programming requires that the corresponding Block Lock-Bit be reset or, if set, that RP#
= VHH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and RP# =
VIH, SR.1 and SR.4 will be set to “1.” Buffered write operations with VIH < RP# < VHH produce
spurious results and should not be attempted.
4.9
Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup
(standard 40H or alternate 10H) is written followed by a second write that specifies the address and
data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and
program verify algorithms internally. After the program sequence is written, the device
automatically outputs status register data when read (see Figure 7, “Byte/Word Program
Flowchart” on page 33). The CPU can detect the completion of the program event by analyzing the
STS pin or status register bit SR.7.
Datasheet
27
INTEL [ INTEL ]
