28F320J5 and 28F640J5
Table 17. Status Register Definition
WSMS
bit 7
ESS
bit 6
ECLBS
bit 5
PSLBS
bit 4
VPENS
bit 3
R
DPS
bit 1
R
bit 2
bit 0
High Z When
Busy?
Status Register Bits
Notes
No
Yes
Yes
Yes
SR.7 = WRITE STATE MACHINE STATUS
Check STS or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR.6–SR.0 are not driven while SR.7 = “0.”
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
If both SR.5 and SR.4 are “1”s after a block
erase or lock-bit configuration attempt, an
improper command sequence was entered.
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.3 does not provide a continuous
programming voltage level indication. The
WSM interrogates and indicates the
programming voltage level only after Block
Erase, Program, Set Block/Master Lock-Bit, or
Clear Block Lock-Bits command sequences.
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
1 = Error in Programming or Set Master/Block
Lock-Bit
0 = Successful Programming or Set Master/Block
Lock Bit
SR.1 does not provide a continuous indication
of master and block lock-bit values. The WSM
interrogates the master lock-bit, block lock-bit,
and RP# only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, dependingon the
Yes
SR.3 = PROGRAMMING VOLTAGE STATUS
1 = Low Programming Voltage Detected,
Operation Aborted
0 = Prog ramming Voltag e OK
attempted operation, if the block lock-bit is set,
Yes
Yes
SR.2 = RESERVED FOR FUTURE ENHANCEMENTS
master lock-bit is set, and/or RP# is not V
Read the block lock and master lock
.
HH
SR.1 = DEVICE PROTECT STATUS
1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock
Detected, Operation Abort
configuration codes using the Read Identifier
Codes command to determine master and
block lock-bit status.
0 = Unlock
Yes
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
SR.2 and SR.0 are reserved for future use
and should be masked when pollingthe status
register.
Table 18. eXtended Status Register Definition
WBS
bit 7
Reserved
bits 6—0
High Z When
Status Register Bits
Busy?
Notes
XSR.7 = WRITE BUFFER STATUS
After a Buffer-Write command, XSR.7 = 1
indicates that a Write Buffer is available.
No
1 = Write buffer available
0 = Write buffer not available
SR.6–SR.0 are reserved for future use and
should be masked when polling the status
register.
XSR.6–XSR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
Yes
Datasheet
31
INTEL [ INTEL ]
