28F320J5 and 28F640J5
Figure 7. Byte/Word Program Flowchart
Start
Bus
Operation
Command
Comments
Setup Byte/
Data = 40H
Write 40H,
Address
Write
Write
Word Program Addr = Location to Be Programmed
Byte/Word
Program
Data = Data to Be Prog rammed
Addr = Location to Be Programmed
Write Data and
Address
Read
(Note 1)
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Read Status
Register
Standby
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuingthe Read Status Register command.
Repeat for subsequent programming operations.
0
SR.7 =
SR full status check can be done after each program operation, or
after a sequence of programming operations.
1
Full Status
Write FFH after the last program operation to place device in read
array mode.
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Read Status
Register Data
(See Above)
Check SR.3
Standby
1 = Programming to Voltage Error
Detect
1
Check SR.1
SR.3 =
SR.1 =
SR.4 =
Voltage Range Error
1 = Device Protect Detect
RP# = VIH, Block Lock-Bit Is Set
Only required for systems
implemetinglock-bit configuration.
Standby
Standby
0
0
0
1
1
Check SR.4
Device Protect Error
Programming Error
1 = Programming Error
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuingthe Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
Byte/Word
Program
Successful
If an error is detected, clear the status register before attempting retry
or other error recovery.
0606_08
Datasheet
33
INTEL [ INTEL ]
