28F320J5 and 28F640J5
4.6
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm. This command sequence requires an appropriate
address within the block to be erased (erase changes all block data to FFH). Block preconditioning,
erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle
block erase sequence is written, the device automatically outputs status register data when read (see
Figure 8, “Block Erase Flowchart” on page 34). The CPU can detect block erase completion by
analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to
update the status register.
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared before system software attempts corrective actions.
The CUI remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are
not accidentally erased. An invalid Block Erase command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when VCC
is valid and VPEN = VPENH. If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will
be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if
set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and
RP# = VIH, SR.1 and SR.5 will be set to “1.” Block erase operations with VIH < RP# < VHH
produce spurious results and should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in
another block of memory. Once the block erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data when read after the Block Erase Suspend
command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase
operation has been suspended (both will be set to “1”). In default mode, STS will also transition to
VOH. Specification tWHRH defines the block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A program command sequence can also be issued during erase suspend to program
data in other blocks. During a program operation with block erase suspended, status register bit
SR.7 will return to “0” and the STS output (in default mode) will transition to VOL
.
The only other valid commands while block erase is suspended are Read Query, Read Status
Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL
.
After the Erase Resume command is written, the device automatically outputs status register data
when read (see Figure 9, “Block Erase Suspend/Resume Flowchart” on page 35). VPEN must
remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. RP#
must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot
resume until program operations initiated during block erase suspend have completed.
26
Datasheet
INTEL [ INTEL ]
