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DT28F320J5-120 参数 Datasheet PDF下载

DT28F320J5-120图片预览
型号: DT28F320J5-120
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏英特尔的StrataFlash ?内存 [5 Volt Intel StrataFlash® Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 51 页 / 620 K
品牌: INTEL [ INTEL ]
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28F320J5 and 28F640J5  
Table 13. Primary Vendor-Specific Extended Query  
Offset(1)  
P = 31h  
Description  
(Optional Flash Features and Commands)  
Hex  
Code  
Length  
Add.  
Value  
(P+0)h  
(P+1)h  
(P+2)h  
(P+3)h  
(P+4)h  
(P+5)h  
(P+6)h  
(P+7)h  
(P+8)h  
3
Primary extended query table  
Unique ASCII string“PRI”  
31:  
32:  
33:  
34:  
35:  
36:  
37:  
38:  
39:  
bit 0 = 0  
bit 1 = 1  
bit 2 = 0  
bit 3 = 1  
bit 4 = 0  
--50  
--52  
--49  
--31  
--31  
--0A  
--00  
--00  
--00  
No  
“P”  
“R”  
“I”  
“1”  
“1”  
1
1
4
Major version number, ASCII  
Minor version number, ASCII  
Optional feature and command support (1=yes, 0=no)  
bits 9–31 are reserved; undefined bits are “0.” If bit 31 is  
“1” then another 31 bit field of optional features follows at  
the end of the bit-30 field.  
bit 0 Chip erase supported  
bit 1 Suspend erase supported  
bit 2 Suspend program supported  
bit 3 Legacy lock/unlock supported  
bit 4 Queued erase supported  
Yes  
No  
Yes  
No  
Supported functions after suspend: read Array, Status,  
Query  
Other supported operations are:  
bits 1–7 reserved; undefined bits are “0”  
bit 0 Program supported after erase suspend  
Block status register mask  
bits 2–15 are Reserved; undefined bits are “0”  
bit 0 Block Lock-Bit Status register active  
bit 1 Block Lock-Down Bit Status active  
(P+9)h  
1
2
3A:  
--01  
bit 0 = 1  
3B:  
3C:  
bit 0 = 1  
bit 1 = 0  
Yes  
--01  
--00  
Yes  
No  
(P+A)h  
(P+B)h  
V
logic supply highest performance program/erase  
CC  
voltage  
bits 0–3 BCD value in 100 mV  
bits 4–7 BCD value in volts  
optimum program/erase supply voltage  
(P+C)h  
1
1
3D:  
--50  
--00  
5.0 V  
0.0 V  
V
PP  
(P+D)h  
(P+E)h  
bits 0–3 BCD value in 100 mV  
bits 4–7 HEX value in volts  
Reserved for Future Use  
3E:  
3F:  
NOTE:  
1. The variable P is a pointer which is defined at CFI offset 15h.  
4.3  
Read Identifier Codes Command  
The identifier code operation is initiated by writing the Read Identifier Codes command. Following  
the command write, read cycles from addresses shown in Figure 5 retrieve the manufacturer,  
device, block lock configuration and master lock configuration codes (see Table 13 for identifier  
code values). To terminate the operation, write another valid command. Like the Read Array  
command, the Read Identifier Codes command functions independently of the VPEN voltage and  
RP# can be VIH or VHH. This command is valid only when the WSM is off or the device is  
suspended. Following the Read Identifier Codes command, the following information can be read:  
24  
Datasheet  
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