28F320J5 and 28F640J5
4.2.5
System Interface Information
The following device information can optimize system interface software.
Table 10. System Interface Information
Hex
Code
Offset Length
Description
Add.
Value
V
V
V
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1Bh
1Ch
1Dh
1Eh
1
1
1
1
1B:
--45
--55
--00
--00
4.5 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1C:
1D:
1E:
5.5 V
0.0 V
0.0 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
1Fh
20h
21h
22h
1
1
1
1
“n” such that typical single word program time-out = 2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
“n” such that typical full chip erase time-out = 2n ms
1F:
20:
21:
22:
--07
--07
--0A
--00
128 µs
128 µs
1 s
NA
“n” such that maximum word program time-out = 2n times
typical
23h
1
23:
--04
2 ms
24h
25h
26h
1
1
1
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
24:
25:
26:
--04
--04
--00
2 ms
16 s
NA
22
Datasheet
INTEL [ INTEL ]
