Host Bridge/DRAM Controller Registers (D0:F0)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
52–53h
GGC
GMCH Graphics Control Register (82915G
GMCH only)
0030h
R/W/L
54–57h
58–8Fh
90h
DEVEN
—
Device Enable
00000019h
—
R/W
—
Reserved
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
PAM6
LAC
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
Programmable Attribute Map 6
Legacy Access Control
00h
00h
00h
00h
00h
00h
00h
00h
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
91h
92h
93h
94h
95h
96h
97h
98–9Bh
9Ch
—
Reserved
TOLUD
SMRAM
Top of Low Usable DRAM
System Management RAM Control
08h
00h
R/W
9Dh
RO,
R/W/L
9Eh
ESMRAMC
Extended System Management RAM Control
00h
RO,
R/W/L
9F–C7h
C8–C9h
—
Reserved
—
—
ERRSTS
Error Status
0000h
RO,
R/W/L
CA–CBh
CC–DBh
DC–DFh
E0–E8h
ERRCMD
—
Error Command
Reserved
0000h
—
R/W
—
SKPD
CAPID0
Scratchpad Data
Capability Identifier
00000000h
R/W
RO
0000000000
01090009h
E9–FFh
100h
—
C0DRB0
C0DRB1
C0DRB2
C0DRB3
—
Reserved
—
00h
00h
00h
00h
—
—
Channel A DRAM Rank Boundary Address 0
Channel A DRAM Rank Boundary Address 1
Channel A DRAM Rank Boundary Address 2
Channel A DRAM Rank Boundary Address 3
Reserved
R/W
R/W
R/W
R/W
—
101h
102h
103h
104–107h
108h
C0DRA0
C0DRA2
—
Channel A DRAM Rank 0,1 Attribute
Channel A DRAM Rank 2,3 Attribute
Reserved
00h
00h
—
R/W
R/W
—
109h
10A–10Bh
10Ch
C0DCLKDIS
—
Channel A DRAM Clock Disable
Reserved
00h
—
R/W
—
10Dh
66
Datasheet
INTEL [ INTEL ]
