Host Bridge/DRAM Controller Registers (D0:F0)
R
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).
Warning: Address locations that are not listed are considered Reserved registers locations. Reads to
Reserved registers may return non-zero values. Writes to reserved locations may cause system
failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are not included in this document. The reserved/unimplemented space in the PCI
configuration header space is not documented as such in this summary.
Table 4-1. Device 0 Function 0 Register Address Map Summary
Address
Offset
Register
Symbol
Default
Value
Register Name
Vendor Identification
Access
00–01h
02–03h
04–05h
06–07h
VID
DID
8086h
2580h
0006h
0090h
RO
RO
Device Identification
PCI Command
PCI Status
PCICMD
PCISTS
RO, R/W
RO,
R/W/C
08h
RID
Revision Identification
See register
description
RO
09–0Bh
0Ch
CC
—
Class Code
060000h
—
RO
—
Reserved
0Dh
MLT
Master Latency Timer
Header Type
00h
RO
0Eh
HDR
—
00h
RO
0F–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
Reserved
—
—
SVID
SID
Subsystem Vendor Identification
Subsystem Identification
Reserved
0000h
0000h
—
R/W/O
R/W/O
—
—
CAPPTR
—
Capabilities Pointer
Reserved
EOh
RO
35–3Fh
40–43h
44–47h
—
—
EPBAR
MCHBAR
Egress Port Base Address
00000000h
00000000h
RO
GMCH Memory Mapped Register Range
Base Address
R/W
48–4Bh
4C–4Fh
PCIEXBAR
DMIBAR
PCI Express* Register Range Base Address
E0000000h
00000000h
R/W
R/W
Root Complex Register Range Base
Address
Datasheet
65
INTEL [ INTEL ]
