Host Bridge/DRAM Controller Registers (D0:F0)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
10E–10F
110–113h
114–117h
118–11Fh
120–123h
124–17Fh
180h
C0BNKARC
—
Channel A DRAM Bank Architecture
Reserved
0000h
R/W
—
—
900122h
—
C0DRT1
—
Channel A DRAM Timing Register
Reserved
R/W
—
C0DRC0
—
Channel A DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
C1DRB0
C1DRB1
C1DRB2
C1DRB3
—
Channel B DRAM Rank Boundary Address 0
Channel B DRAM Rank Boundary Address 1
Channel B DRAM Rank Boundary Address 2
Channel B DRAM Rank Boundary Address 3
Reserved
00h
R/W
R/W
R/W
R/W
—
181h
00h
182h
00h
183h
00h
184–187h
188h
—
C1DRA0
C1DRA2
—
Channel B DRAM Rank 0,1 Attribute
Channel B DRAM Rank 2,3 Attribute
Reserved
00h
R/W
R/W
—
189h
00h
18A–18Bh
18Ch
—
C1DCLKDIS
—
Channel B DRAM Clock Disable
Reserved
00h
R/W
—
18Dh
—
18E–18Fh
190–193h
194h
C1BNKARC
—
Channel B Bank Architecture
Reserved
0000h
—
R/W
—
C1DRT1
—
Channel B DRAM Timing Register 1
Reserved
900122h
—
R/W, RO
—
195–19Fh
1A0–1A3h
1A4–F0Fh
F10–F13h
F14h
C1DRC0
—
Channel B DRAM Controller Mode 0
Reserved
00000000h
—
R/W, RO
—
PMCFG
PMSTS
Power Management Configuration
Power Management Status
00000000h
00000000h
R/W
R/W/C/S
Datasheet
67
INTEL [ INTEL ]
