Register Description
R
3.3.5
Intel® 915x GMCH Configuration Cycle Flowchart
Figure 3-6. Intel® 915x GMCH Configuration Cycle Flowchart
DW I/O Write to
CONFIG_ADDRES
S with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Yes
Bus# = 0
No
GMCH Generates
Type 1 Access to
PCI Express
Bus# > Sec Bus
Bus# ≤ Sub Bus
in GMCH Dev 1
GMCH Claims if
Function# = 0
Yes
Yes
Device# = 0
No
No
Bus# =
Yes
Secondary Bus in
GMCH Dev 1
Yes
Yes
Yes
Device# = 1 &
Dev # 1 Enabled
GMCH Claims if
Function# = 0
No
No
GMCH Generates MISI
Type 1Configuration
Cycle
Device# = 2 &
Dev# 2
Enabled
GMCH Claims if
Function# = 0
No
GMCH Generates
Type 0 Accessto
PCI Express
Device# = 7&
Dev# 7 Enabled
Yes
Device# = 0
GMCH Claims if
Function# = 0
No
No
MCH allows cycle to
go to DMI resulting in
Master Abort
GMCH Generates DMI
Type 0 Configuration
Cycle
Config_Cyc_Flow_915
62
Datasheet
INTEL [ INTEL ]
