Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.31
PEG_CAPL—PCI Express* Capability List (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A0h
0010h
RO
Size:
16 bits
This register enumerates the PCI Express capability structure.
Bit
Access &
Default
Description
15:8
RO
00h
Pointer to Next Capability: This value terminates the capabilities list. The Virtual
Channel capability and any other PCI Express* specific capabilities that are
reported via this mechanism are in a separate capabilities list located entirely
within PCI Express extended configuration space.
7:0
RO
Capability ID: This field identifies this linked list item (capability structure) as
10h
being for PCI Express registers.
8.1.32
PEG_CAP—PCI Express*-G Capabilities (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
A2h
0141h
RO
Size:
16 bits
Indicates PCI Express device capabilities.
Bit
Access &
Default
Description
15:14
13:9
Reserved
RO
Interrupt Message Number: Hardwired to 0.
00h
8
R/WO
1b
Slot Implemented
0 = The PCI Express* Link associated with this port is connected to an integrated
component or is disabled.
1 = The PCI Express Link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
7:4
3:0
RO
4h
Device/Port Type: Hardwired to 0100 to indicate root port of PCI Express Root
Complex.
RO
1h
PCI Express Capability Version: Hardwired to 1 as it is the first version.
150
Datasheet
INTEL [ INTEL ]
