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82915GV 参数 Datasheet PDF下载

82915GV图片预览
型号: 82915GV
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 426 页 / 3241 K
品牌: INTEL [ INTEL ]
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Host-PCI Express* Bridge Registers (D1:F0)  
(Intel® 82915G/82915P/82915PL Only)  
R
8.1.36  
LCAP—Link Capabilities (D1:F0)  
PCI Device:  
Address Offset:  
Default Value:  
Access:  
1
ACh  
02012E01h  
R/WO  
16 bits  
Size:  
This register indicates PCI Express device specific capabilities.  
Bit  
Access &  
Default  
Description  
31:24  
RO  
Port Number: This field indicates the PCI Express* port number for the given PCI  
02h  
Express link. This field matches the value in Element Self Description [31:24].  
23:18  
17:15  
Reserved  
R/WO  
010b  
L1 Exit Latency: This field indicates the length of time this Port requires to  
complete the transition from L1 to L0. The value 010 b indicates the range of 2 µs  
to less than 4 µs. If this field is required to be any value other than the default,  
BIOS must initialize it accordingly.  
Both bytes of this register that contain a portion of this field must be written  
simultaneously in order to prevent an intermediate (and undesired) value from  
ever existing.  
14:12  
R/WO  
010b  
L0s Exit Latency: This field indicates the length of time this Port requires to  
complete the transition from L0s to L0. The value 010 b indicates the range of 128  
ns to less than 256 ns. If this field is required to be any value other than the  
default, BIOS must initialize it accordingly.  
Note: When PCI Express* is operating with separate reference clocks, L0s exit  
latency may be greater than the setting in the L0s Exit Latency Register.  
Expect longer exit latency then setting in L0s Exit Latency Register. The  
link may enter Recovery state before reaching L0. System BIOS can  
program the appropriate Exit Latency and advertised N_FTS value if it  
detects that the downstream device is not using the common reference  
clock (indicated in the Slot Clock Configuration bit 12 of the device’s Link  
Status Register)  
11:10  
9:4  
R/WO  
11b  
Active State Link PM Support: L0s & L1 entry supported.  
RO  
Max Link Width: Hardwired to indicate X16.  
10h  
When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface  
device, this field reflects X1 (01h).  
3:0  
RO  
1h  
Max Link Speed: Hardwired to indicate 2.5 Gb/s.  
154  
Datasheet  
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