Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.27
MSI_CAPID—Message Signaled Interrupts Capability ID
(D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
90h
A005h
RO
Size:
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by writing a
predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH (CAPL [0] at
7Fh). In that case walking this linked list will skip this capability and, instead, go directly from
the PCI PM capability to the PCI Express capability.
Bit
15:8
7:0
Access &
Default
Description
RO
A0h
Pointer to Next Capability: This field contains a pointer to the next item in the
capabilities list that is the PCI Express* capability.
RO
Capability ID:
05h
05h = Identifies this linked list item (capability structure) as being for MSI
registers.
Datasheet
147
INTEL [ INTEL ]
