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82915GV 参数 Datasheet PDF下载

82915GV图片预览
型号: 82915GV
PDF下载: 下载PDF文件 查看货源
内容描述: Express芯片组 [Express Chipset]
分类和应用:
文件页数/大小: 426 页 / 3241 K
品牌: INTEL [ INTEL ]
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Host-PCI Express* Bridge Registers (D1:F0)  
(Intel® 82915G/82915P/82915PL Only)  
R
8.1.23  
PM_CAPID1—Power Management Capabilities (D1:F0)  
PCI Device:  
Address Offset:  
Default Value:  
Access:  
1
80h  
1902 9001h or 1902 A001h  
RO  
Size:  
32 bits  
Bit  
Access &  
Default  
Description  
31:27  
RO  
19h  
PME Support: This field indicates the power states in which this device may  
indicate PME wake via PCI Express messaging. D0, D3hot, and D3cold. This  
device is not required to do anything to support D3hot and D3cold; it simply must  
report that those states are supported. Refer to the PCI Power Management 1.1  
specification for encoding explanation and other power management details.  
26  
25  
RO  
0b  
D2: Hardwired to 0 to indicate that the D2 power management state is NOT  
supported.  
RO  
0b  
D1: Hardwired to 0 to indicate that the D1 power management state is NOT  
supported.  
24:22  
21  
RO  
000b  
Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary  
current requirements.  
RO  
0 b  
Device Specific Initialization (DSI): Hardwired to 0 to indicate that special  
initialization of this device is NOT required before generic class device driver is to  
use it.  
20  
19  
RO  
0b  
Auxiliary Power Source (APS): Hardwired to 0.  
RO  
0b  
PME Clock: Hardwired to 0 to indicate this device does NOT support PME#  
generation.  
18:16  
RO  
010b  
PCI PM CAP Version: Hardwired to 02h to indicate there are 4 bytes of power  
management registers implemented and that this device complies with revision  
1.1 of the PCI Power Management Interface Specification.  
15:8  
7:0  
RO  
90h  
or  
Pointer to Next Capability: This field contains a pointer to the next item in the  
capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the  
capabilities list is the Message Signaled Interrupts (MSI) capability at 90h. If  
MSICH (CAPL[0] @ 7Fh) is 1, then the next item in the capabilities list is the PCI  
Express* capability at A0h.  
A0h  
RO  
Capability ID: Value of 01h identifies this linked list item (capability structure) as  
01h  
being for PCI Power Management registers.  
144  
Datasheet  
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