Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.24
PM_CS1—Power Management Control/Status (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
84h
00000000h
RO, R/W/S
32 bits
Size:
Bit
Access &
Default
Description
31:16
15
Reserved
PME Status: This bit indicates that this device does not support PME#
RO
0b
generation from D3
.
cold
14:13
12:9
8
RO
00b
Data Scale: This field indicates that this device does not support the power
management data register.
RO
0h
Data Select: This field indicates that this device does not support the power
management data register.
R/W/S
0b
PME Enable: This bit indicates that this device does not generate PMEB
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
1:0
Reserved
R/W
00b
Power State: This field indicates the current power state of this device and can
be used to set the device into a new power state. If software attempts to write an
unsupported state to this field, write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state to be fully functional.
There is no hardware functionality required to support these power states.
Datasheet
145
INTEL [ INTEL ]
