Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.10
SBUSN1—Secondary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
19h
00h
RO
8 bits
Size:
This register identifies the bus number assigned to the second bus side of the “virtual” bridge i.e.
to PCI Express Graphics. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express Graphics.
Bit
Access &
Default
Description
7:0
R/W
00h
Secondary Bus Number (BUSN): This field is programmed by configuration
software with the bus number assigned to PCI Express*-G.
8.1.11
SUBUSN1—Subordinate Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
1Ah
00h
R/W
8 bits
Size:
This register identifies the subordinate bus (if any) that resides at the level below PCI Express
Graphics. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to PCI Express Graphics.
Bit
Access &
Default
Description
7:0
R/W
00h
Subordinate Bus Number (BUSN): This register is programmed by
configuration software with the number of the highest subordinate bus that lies
behind the device 1 bridge. When only a single PCI device resides on the PCI
Express*-G segment, this register will contain the same value as the SBUSN1
register.
134
Datasheet
INTEL [ INTEL ]
