Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Bit
12
Access &
Default
Description
RO
0b
Received Target Abort Status (RTAS): Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
11
RO
0b
Signaled Target Abort Status (STAS): Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
10:9
RO
00b
DEVSELB Timing (DEVT): This device is not the subtractive decoded device on
bus 0. This bit field is therefore hardwired to 00b to indicate that the device uses
the fastest possible decode.
8
RO
0b
Master Data Parity Error (PMDPE): Because the primary side of the PCI
Express* x16 Graphics Interface’s virtual PCI-to-PCI bridge is integrated with the
(G)MCH functionality, there is no scenario where this bit will get set. Because
hardware will never set this bit, it is impossible for software to have an
opportunity to clear this bit or otherwise test that it is implemented. The PCI
specification defines it as a R/WC; however, for this implementation, an RO
definition behaves the same way and will meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
7
RO
0b
Fast Back-to-Back (FB2B): Hardwired to 0.
6
5
Reserved
RO
0b
66/60MHz capability (CAP66): Hardwired to 0.
4
3
RO
1b
Capabilities List: This bit indicates that a capabilities list is present. Hardwired
to 1.
RO
0b
INTA Status: This field indicates that an interrupt message is pending internally
to the device. Only PME and Hot Plug sources feed into this status bit (not PCI
INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit,
PCICMD1[10], has no effect on this bit.
2:0
Reserved
Datasheet
131
INTEL [ INTEL ]
