Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.7
CL1—Cache Line Size (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Ch
00h
R/W
8 bits
Size:
Bit
Access &
Default
Description
7:0
R/W
00h
Cache Line Size (Scratch pad): This field is implemented by PCI Express*
devices as a read/write field for legacy compatibility purposes but has no impact
on any PCI Express device functionality.
8.1.8
HDR1—Header Type (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
0Eh
01h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical register exists at
this location.
Bit
Access &
Default
Description
7:0
RO
Header Type Register (HDR): This field returns 01h to indicate that this is a
01h
single function device with bridge header layout.
8.1.9
PBUSN1—Primary Bus Number (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
18h
00h
RO
8 bits
Size:
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus 0.
Bit
Access &
Default
Description
7:0
RO
00h
Primary Bus Number (BUSN): Configuration software typically programs this
field with the number of the bus on the primary side of the bridge. Since device 1
is an internal device and its primary bus is always 0, these bits are read only and
are hardwired to 0.
Datasheet
133
INTEL [ INTEL ]
