Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
8.1.5
RID1—Revision Identification (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
08h
See bit description
RO
Size:
8 bits
This register contains the revision number of the (G)MCH device 1.
Bit
Access &
Default
Description
7:0
RO
00h
Revision Identification Number (RID1): This field indicates the number of times
that this device in this component has been “stepped” through the manufacturing
process. Refer to the Intel®
82915G/82915P/82915PL/82915GV/82915GL/82910GL Express Chipset
Specification Update for the value of the Revision ID Register.
8.1.6
CC1—Class Code (D1:F0)
PCI Device:
Address Offset:
Default Value:
Access:
1
09h
060400h
RO
Size:
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a register-
specific programming interface.
Bit
Access &
Default
Description
23:16
RO
Base Class Code (BCC): This field indicates the base class code for this
06h
device.
06h = Bridge device.
15:8
7:0
RO
04h
Sub-Class Code (SUBCC): This field indicates the sub-class code for this
device.
04h = PCI-to-PCI Bridge.
RO
00h
Programming Interface (PI): This field indicates the programming interface of
this device. This value does not specify a particular register set layout and
provides no practical use for this device.
132
Datasheet
INTEL [ INTEL ]
