Host-PCI Express* Bridge Registers (D1:F0)
(Intel® 82915G/82915P/82915PL Only)
R
Address
Offset
Register
Symbol
Default
Value
Register Name
Access
B2–B3h
B4–B7h
B8–B9h
BA–BBh
BC–BDh
BE–BFh
C0–C3h
C4–EBh
EC–EFh
F0–FFh
100–103h
LSTS
SLOTCAP
SLOTCTL
SLOTSTS
RCTL
Link Status
1001h
00000000h
01C0h
0X00h
RO
R/WO
R/W
Slot Capabilities
Slot Control
Slot Status
RO, R/W/C
R/W
Root Control
0000h
—
Reserved
—
—
RSTS
Root Status
00000000h
—
RO, R/W/C
—
—
Reserved
PEGLC
—
PCI Express*-Graphics Legacy Control
Reserved
00000000h
—
R/W, RO
—
VCECH
Virtual Channel Enhanced Capability
Header
14010002h
RO
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–11Fh
120–123h
124–125h
126–127h
128–13Fh
140–143h
PVCCAP1
PVCCAP2
PVCCTL
—
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
00000001h
00000001h
0000h
RO, R/WO
RO
R/W
—
Reserved
—
VC0RCAP
VC0RCTL
—
VC0 Resource Capability
VC0 Resource Control
Reserved
00000000h
8000007Fh
—
RO
RO, R/W
—
VC0RSTS
VC1RCAP
VC1RCTL
—
VC0 Resource Status
VC1 Resource Capability
VC1 Resource Control
Reserved
0000h
RO
00008000h
01000000h
—
RO
RO, R/W
—
VC1RSTS
—
VC1 Resource Status
Reserved
0000h
RO
—
—
RCLDECH
Root Complex Link Declaration Enhanced
Capability Header
00010005h
RO
144–147h
148–14Fh
150–153h
154–157h
158–15Fh
ESD
—
Element Self Description
Reserved
02000100h
RO, R/WO
—
—
00000000h
—
LE1D
—
Link Entry 1 Description
Reserved
RO, R/WO
—
LE1A
Link Entry 1 Address
000000000
0000000h
R/WO
160–217h
218–21Fh
—
Reserved
—
—
PEGSSTS
PCI Express*-Graphics Sequence Status
000000000
0000FFFh
RO
220–FFFh
—
Reserved
—
—
Datasheet
127
INTEL [ INTEL ]
