Networking Silicon — 82551IT
9.3.13
Register 28: MDI/MDI-X Control Register
Table 43. Register 28: MDI/MDI-X Control
Bit(s)
Name
Reserved
Definition
Default
R/W
R/W
15:8
Reserved for future use. Set these bits to 0.
0
0
Enables the MDI/MDI-X feature (writing to this bit
overwrites the default value).
Auto Switch
Enable
7
R/W
1 = Enabled.
0 = Disabled.
Manual switch (valid only if bit 7 is set to 0).
1 = Forces the port to be MDI-X (cross-over).
0 = Forces the port to be MDI (straight-through)
6
5
4
Switch
Status
0
0
1
R/W
RO
RO
Indicates the state of the MDI pair.
1 = MDI-X (cross-over).
0 = MDI (straight-through).
Indicates when the correct configuration is achieved.
1 = Resolution algorithm has completed.
Auto Switch
Complete
0 = Resolution algorithm has not completed.
Defines the minimum slot time the algorithm uses in
order to switch between one configuration or another.
3:0
Resolution Timer
0000
R/W
0000 = 80ms.
1111 = 105ms.
9.3.14
Register 29: Hardware Integrity Control Register
Table 44. Register 29: Hardware Integrity Control
Bit(s)
15
Name
Description
Default
R/W
HWI Enable
This bit enables the HWI feature causing the PHY unit
to enter HWI test mode.
0
RW
1 = HWI enabled
0 = HWI disabled
14
13
Ability Check
Test Execute
This bit reports the results of the HWI ability check
and is valid 100 µs after the HWI Enabled bit (bit 15 of
this register) is set (1b).
RO
1 = Test passed
0 = Test failed (HWI ability not detected)
When this bit is set, the PHY unit launches test pulses
on the wire to determine the distance to the cable’s
high or low impedance point.
WO
1 = Execute test
0 = Do not execute test
Datasheet
69
INTEL [ INTEL ]
