82551IT — Networking Silicon
10.2.2
XOR Tree
The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the
placement of the 82551IT to be validated at board test. The XOR Tree was chosen for its speed
advantages. Modern automated test equipment can perform a complete peripheral scan without
support at the board level. This command connects all outputs of the input buffers in the device
periphery into a XOR Tree scheme. All the output drivers of the output buffers, except the Test Port
Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of the
tree. There are two separate chains and associated outputs for speed. Any hard strapped pins will
prevent the tester from scanning correctly. This mode is entered by placing the test pins in the
following combination:
TEST = 1
TEXEC = 1
TI = 1
TCK = 0
ISOLATE# = 1
Note: ISOLATE# must be driven high in order to enter test mode and must be kept high throughout the
entire test.
There are two XOR Tree chains with two separate outputs assigned to FLOE# (Chain 1) and
FLWE# (Chain 2).
Table 45. XOR Tree Chains
Chain Order
(XOR Tree Output)
Chain 1
(FLOE#)
Chain 2
(FLWE#)
1
2
RST#
IDSEL
REQ#
LILED#
ACTLED#
SPDLED#
3
4
AD[23]
SERR#
AD[22]
AD[21]
AD[20]
AD[19]
AD[18]
AD[17]
C/BE#[2]
FRAME#
IRDY#
TRDY#
CLK
5
6
7
8
ALTRST#
CLK_RUN#
AD[31]
9
10
11
12
13
14
15
16
17
18
19
20
21
AD[30]
AD[29]
AD[28]
AD[27]
PME#
DEVSEL#
INTA#
AD[26]
AD[25]
C/BE#[3]
AD[24]
FLD0
STOP#
GNT#
PERR#
72
Datasheet
INTEL [ INTEL ]
