Networking Silicon — 82551IT
9.3.5
Register 20: 100BASE-TX Receive Disconnect Counter
Table 35. Register 20: 100BASE-TX Receive Disconnect Counter
Bit(s)
Name
Description
Default
R/W
15:0
Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter freezes when full
and self-clears on read
--
RO
SC
9.3.6
Register 21: 100BASE-TX Receive Error Frame Counter
Table 36. Register 21: 100BASE-TX Receive Error Frame Counter
Bit(s)
Name
Description
Default
R/W
15:0
Receive Error
Frame
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter freezes when full and self-clears
on read.
--
RO
SC
9.3.7
Register 22: Receive Symbol Error Counter
Table 37. Register 22: Receive Symbol Error Counter
Bit(s)
Name
Description
Default
R/W
15:0
Symbol Error
Counter
This field contains a 16-bit counter that increments for
each symbol error. The counter freezes when full and
self-clears on read.
--
RO
SC
In a frame with a bad symbol, each sequential six bad
symbols count as one.
9.3.8
Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter
Table 38. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit(s)
Name
Description
Default
R/W
15:0
Premature End of This field contains a 16-bit counter that increments for
--
RO
SC
Frame
each premature end of frame event. The counter
freezes when full and self-clears on read.
9.3.9
Register 24: 10BASE-T Receive End of Frame Error Counter
Table 39. Register 24: 10BASE-T Receive End of Frame Error Counter
Bit(s)
Name
Description
Default
R/W
15:0
End of Frame
Counter
This is a 16-bit counter that increments for each end
of frame error event. The counter freezes when full
and self-clears on read.
--
RO
SC
Datasheet
67
INTEL [ INTEL ]
