82551IT — Networking Silicon
Table 32. Register 17: PHY Unit Special Control
Bit(s)
12
Name
Description
Default
R/W
RW
Force 34
1 = Force 34 transmit pattern
0
Transmit Pattern
Good Link
0 = Normal operation
11
1 = 100BASE-TX link good
0 = Normal operation
0
RW
10
9
Reserved
This bit is reserved and should be set to 0b.
0
0
RW
RW
Transmit Carrier
Sense Disable
1 = Transmit Carrier Sense disabled
0 = Transmit Carrier Sense enabled
8
7
6
5
4
3
2
1
0
Disable Dynamic 1 = Dynamic Power-Down disabled
0
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
Power-Down
0 = Dynamic Power-Down enabled (normal)
Auto-Negotiation
Loopback
1 = Auto-Negotiation loopback
0 = Auto-Negotiation normal mode
MDI Tri-State
Filter By-pass
1 = MDI Tri-state (transmit driver tri-states)
0 = Normal operation
1 = By-pass filter
0 = Normal filter operation
Auto Polarity
Disable
1 = Auto Polarity disabled
0 = Normal polarity operation
Squelch Disable
1 = 10BASE-T squelch test disable
0 = Normal squelch operation
Extended
Squelch
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
Link Integrity
Disable
1 = Link disabled
0 = Normal Link Integrity operation
Jabber Function
Disable
1 = Jabber disabled
0 = Normal Jabber operation
9.3.3
9.3.4
Register 18: PHY Address Register
Table 33. Register 18: PHY Address
Bit(s)
15:5
Name
Reserved
Description
Default
R/W
These bits are reserved and should be set to a
constant ‘0’
0
RO
RO
4:0
PHY Address
These bits are set to the PHY’s address, 00001b.
1
Register 19: 100BASE-TX Receive False Carrier Counter
Table 34. Register 19: 100BASE-TX Receive False Carrier Counter
Bit(s)
Name
Description
Default
R/W
15:0
Receive False
Carrier
These bits are used for the false carrier counter.
--
RO
SC
66
Datasheet
INTEL [ INTEL ]
