82551IT — Networking Silicon
9.3.10
Register 25: 10BASE-T Transmit Jabber Detect Counter
Table 40. Register 25: 10BASE-T Transmit Jabber Detect Counter
Bit(s)
Name
Description
Default
R/W
15:0
Jabber Detect
Counter
This is a 16-bit counter that increments for each
jabber detection event. The counter freezes when full
and self-clears on read.
--
RO
SC
9.3.11
Register 26: Equalizer Control and Status Register
Table 41. Register 26: Equalizer Control and Status
Bit(s)
Name
Reserved
Description
Reserved for future use
Default
R/W
RW
15:0
--
9.3.12
Register 27: PHY Unit Special Control Register
Table 42. Register 27: PHY Unit Special Control
Bit(s)
Name
Reserved
Description
Default
R/W
15:3
2:0
These bits are reserved and should be set to 0b.
0
RW
RW
LED Switch
Control
Value
000
001
010
011
100
101
110
111
ACTLED# LILED#
000
Activity
Speed
Speed
Activity
Off
Link
Collision
Link
Collision
Off
Off
On
On
Off
On
On
68
Datasheet
INTEL [ INTEL ]
