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80960JD-40 参数 Datasheet PDF下载

80960JD-40图片预览
型号: 80960JD-40
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式32位微处理器 [EMBEDDED 32-BIT MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 61 页 / 1555 K
品牌: INTEL [ INTEL ]
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80960JD  
A
Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)  
NAME  
BE3:0  
TYPE  
DESCRIPTION  
O
BYTE ENABLES select which of up to four data bytes on the bus participate in the  
current bus access. Byte enable encoding is dependent on the bus width of the  
memory region accessed:  
R(1)  
H(Z)  
P(1)  
32-bit bus:  
BE3 enables data on AD31:24  
BE2 enables data on AD23:16  
BE1 enables data on AD15:8  
BE0 enables data on AD7:0  
16-bit bus:  
BE3 becomes Byte High Enable (enables data on AD15:8)  
BE2 is not used (state is high)  
BE1 becomes Address Bit 1 (A1)  
BE0 becomes Byte Low Enable (enables data on AD7:0)  
8-bit bus:  
BE3 is not used (state is high)  
BE2 is not used (state is high)  
BE1 becomes Address Bit 1 (A1)  
BE0 becomes Address Bit 0 (A0)  
The processor asserts byte enables, byte high enable and byte low enable during T .  
a
Since unaligned bus requests are split into separate bus transactions, these signals  
do not toggle during a burst. They remain active through the last Td cycle.  
For accesses to 8- and 16-bit memory, the processor asserts the address bits in  
conjunction with A3:2 described above.  
WIDTH/  
O
WIDTH/HALTED signals denote the physical memory attributes for a bus transaction:  
HLTD1:0  
R(0)  
H(Z)  
P(1)  
WIDTH/HLTD1  
WIDTH/HLTD0  
0
0
1
1
0
1
0
1
8 Bits Wide  
16 Bits Wide  
32 Bits Wide  
Processor Halted  
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in  
response to a HOLD request, regardless of prior operating state.  
D/C  
O
DATA/CODE indicates that a bus access is a data access (1) or an instruction access  
R(X)  
H(Z)  
P(Q)  
(0). D/C has the same timing as W/R.  
0 = instruction access  
1 = data access  
W/R  
O
WRITE/READ specifies, during a T cycle, whether the operation is a write (1) or read  
a
R(0)  
H(Z)  
P(Q)  
(0). It is latched on-chip and remains valid during T cycles.  
d
0 = read  
1 = write  
8
PRELIMINARY