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80960JD-40 参数 Datasheet PDF下载

80960JD-40图片预览
型号: 80960JD-40
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式32位微处理器 [EMBEDDED 32-BIT MICROPROCESSOR]
分类和应用: 微处理器
文件页数/大小: 61 页 / 1555 K
品牌: INTEL [ INTEL ]
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A
80960JD  
Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)  
NAME  
DT/R  
TYPE  
DESCRIPTION  
O
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the  
R(0)  
H(Z)  
P(Q)  
address/data bus. It is low during Ta and Tw/T cycles for a read; it is high during T  
a
d
and Tw/T cycles for a write. DT/R never changes state when DEN is asserted.  
d
0 = receive  
1 = transmit  
DEN  
O
DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted  
at the start of the first data cycle in a bus access and deasserted at the end of the last  
data cycle. DEN is used with DT/R to provide control for data transceivers connected  
to the data bus.  
R(1)  
H(Z)  
P(1)  
0 = data cycle  
1 = not data cycle  
BLAST  
RDYRCV  
O
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the  
last data transfer of burst and non-burst accesses. BLAST remains active as long as  
wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final  
data transfer in a bus cycle.  
R(1)  
H(Z)  
P(1)  
0 = last data transfer  
1 = not last data transfer  
I
READY/RECOVER indicates that data on AD lines can be sampled or removed. If  
S(L)  
RDYRCV is not asserted during a T cycle, the Td cycle is extended to the next cycle  
by inserting a wait state (T ).  
w
d
0 = sample data  
1 = don’t sample data  
The RDYRCV pin has another function during the recovery (Tr) state. The processor  
continues to insert additional recovery states until it samples the pin HIGH. This  
function gives slow external devices more time to float their buffers before the  
processor begins to drive address again.  
0 = insert wait states  
1 = recovery complete  
LOCK/  
ONCE  
I/O  
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The  
LOCK output is asserted in the first clock of an atomic operation and deasserted in  
the last data transfer of the sequence. The processor does not grant HOLDA while it  
is asserting LOCK. This prevents external agents from accessing memory involved in  
semaphore operations.  
S(L)  
R(H)  
H(Z)  
P(1)  
0 = Atomic read-modify-write in progress  
1 = Atomic read-modify-write not in progress  
ONCE MODE: The processor samples the ONCE input during reset. If it is asserted  
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the  
processor stops all clocks and floats all output pins. The pin has a weak internal  
pullup which is active during reset to ensure normal operation when the pin is left  
unconnected.  
0 = ONCE mode enabled  
1 = ONCE mode not enabled  
9
PRELIMINARY