80960JD
A
natively, mark and fmark instructions can generate
trace events explicitly in the instruction stream.
Hardware breakpoint registers are also available to
trap on execution and data addresses.
between various components are correct, and
various components interact correctly on the printed
circuit board.
The JTAG Boundary Scan feature is an attractive
alternative to conventional “bed-of-nails” testing. It
can examine connections which might otherwise be
inaccessible to a test system.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-
micron manufacturing process. The processor’s sub-
micron topology provides the circuit density for
optimal cache size and high operating speeds while
dissipating modest power. The processor also uses
dynamic power management to turn off clocks to
unused circuits.
2.9
Memory-Mapped Control
Registers
The 80960JD, though compliant with i960 series
processor core, has the added advantage of
memory-mapped, internal control registers not found
on the i960 Kx, Sx or Cx processors. These give
software the interface to easily read and modify
internal control registers.
Users may program the 80960Jx to enter Halt mode
for maximum power savings. In Halt mode, the
processor core stops completely while the integrated
peripherals continue to function, reducing overall
power requirements up to 90 percent. Processor
execution resumes from internally or externally
generated interrupts.
Each of these registers is accessed as a memory-
mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.
2.8
Test Features
The 80960Jx incorporates numerous features which
enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Scan (JTAG).
2.10 Data Types and Memory
Addressing Modes
As with all i960 family processors, the 80960Jx
instruction set supports several data types and
formats:
The 80960Jx provides testability features compatible
with IEEE Standard Test Access Port and Boundary
Scan Architecture (IEEE Std. 1149.1).
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This
feature allows a mounted 80960JD to electrically
“remove” itself from a circuit board. This allows for
system-level testing where a remote tester — such
The 80960Jx provides a full set of addressing modes
for C and assembly programming:
• Two Absolute modes
as an in-circuit emulator
processor system.
— can exercise the
• Five Register Indirect modes
• Index with displacement
• IP with displacement
The provided test logic does not interfere with
component or circuit board behavior and ensures
that components function correctly, connections
4
PRELIMINARY
INTEL [ INTEL ]
