®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY
The mobile Pentium processor with MMX
The code cache, branch target buffer and prefetch
technology is both software and pin compatible with
previous members of the mobile Pentium processor
family. It contains 4.5 million transistors and is
manufactured on lntel's enhanced 0.35 micron
buffers are responsible for getting raw instructions
into the execution units of the mobile Pentium
processor. Instructions are fetched from the code
cache or from the external bus. Branch addresses
are remembered by the branch target buffer. The
code cache TLB translates linear addresses to
physical addresses used by the code cache.
(120/133/150/166
MHz)
or
0.25
micron
(166/200/233/266 MHz) CMOS process which
allows voltage reduction technology for low power
and high density. This enables the mobile Pentium
processor with MMX technology to remain within
the thermal envelope while providing a significant
performance increase.
The decode unit decodes the prefetched
instructions so the mobile Pentium processor can
execute the instruction. The control ROM contains
the microcode which controls the sequence of
operations that must be performed to implement the
mobile Pentium processor architecture. The control
ROM unit has direct control over both pipelines.
In addition to the architecture described in the
previous section for the mobile Pentium processor
family, the mobile Pentium processor with MMX
technology
has
several
additional
micro-
architectural enhancements, which are described
below.
The mobile Pentium processor contains a pipelined
floating-point unit that provides
a
significant
floating-point performance advantage over previous
generations of processors.
2.2.1. Full support for Intel MMX TM technology
MMX technology is based on SIMD technique
(Single Instruction, Multiple Data) which enables
In addition to the SMM features described above,
the mobile Pentium processor supports clock
control. When the clock to the processor is stopped,
power dissipation is virtually eliminated. The
combination of these improvements makes the
increased performance on
a wide variety of
multimedia and communications applications. Fifty-
seven new instructions and four new 64-bit data
types are supported in the mobile Pentium
processor with MMX technology. All existing
operating system and application software are fully-
compatible.
mobile Pentium processor
a good choice for
energy-efficient notebook designs.
The mobile Pentium processor supports fractional
bus operation. This allows the internal processor
core to operate at high frequencies, while
communicating with the external bus at lower
frequencies.
2.2.2. Doubled code / data caches to 16K each
On-chip level-1 data and code cache sizes have
been doubled to 16KB each and are 4-way set
associative on the mobile Pentium processor with
MMX technology. Larger separate internal caches
improve performance by reducing average memory
access time and providing fast access to recently-
used instructions and data. The instruction and data
caches can be accessed simultaneously while the
data cache supports two data references
simultaneously. The data cache supports a write-
back (or alternatively, write-through, on a line by
line basis) policy for memory updates.
The mobile Pentium® processor with MMX™
technology on 0.25 micron contains an on-chip
advanced programmable interrupt controller (APIC).
This function is reserved for future multi-processing
function.
The architectural features introduced in this section
are more fully described in the Pentium® Processor
Family Developer's Manual (Order Number:
241428).
®
2.2.3. Improved branch prediction
2.2.
Mobile Pentium Processor
TM
with MMX Technology
Dynamic branch prediction uses the Branch Target
Buffer (BTB) to boost performance by predicting the
most likely set of instructions to be executed. The
BTB has been improved on the mobile Pentium
processor with MMX technology to increase its
accuracy. Further, this processor has four prefetch
The mobile Pentium processor with MMX
technology is a significant addition to the mobile
Pentium processor family. Available at 120, 133,
150, 166, 200, 233, and 266 MHz, it is the first
microprocessor to support Intel MMX technology.
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INTEL [ INTEL ]
