MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
2.0.
1.0.
INTRODUCTION
MICROPROCESSOR
ARCHITECTURE OVERVIEW
The mobile Pentium® processors with MMX™
technology on 0.25 micron
are fully compatible
with the existing mobile Pentium processors with
MMX technology (120, 133, 150, & 166 MHz) with
the following differences: voltage supplies, power
consumption,
and
performance.
These
processors, when used in a TCP package, are
socket compatible with the mobile Pentium
processor (75, 90, 100, 120, 133, 150 MHz)
making it possible to design a flexible motherboard
that supports both the mobile Pentium processor
(75 MHz - 150 MHz) and the mobile Pentium
processor with MMX technology (120
MHz - 266
MHz). It has all the advanced features of the
desktop version of the Pentium processor with
MMX technology except for the differences listed
in Section 3.1.
The mobile Pentium processor with MMX
technology on 0.25 micron
has several features
which allow high-performance notebooks to be
designed, including the following:
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TCP dimensions are ideal for small form-factor
designs.
TCP has superior thermal resistance
characteristics.
1.8V (166/200/233 MHz)/2.0V (266 MHz)
core
and 2.5V I/O buffer V
CC
inputs reduce power
consumption significantly.
The SL Enhanced feature set.
The mobile Pentium processor with MMX
technology on 0.25 micron
extends the mobile
Pentium processor with MMX technology family. It
is binary compatible with the 8086/88™ , 80286™ ,
Intel386™ DX, Intel386 SX, Intel486™ DX,
Intel486 SX, Intel486 DX2, and mobile Pentium
processors with voltage reduction technology (75-
150).
The mobile Pentium processor family consists of
the mobile Pentium processor with MMX
technology (120,
133, 150, & 166), The mobile
Pentium processor with MMX technology on 0.25
micron (166, 200, 233, & 266)
and the mobile
Pentium processor with voltage reduction
technology (75 MHz -150 MHz).
The mobile Pentium processor with MMX
technology
on 0.25 micron
contains all of the
features of previous Intel Architecture and
provides significant enhancements and additions
including the following:
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•
•
•
•
•
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•
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Support for MMX™ Technology
Superscalar Architecture
Enhanced Branch Prediction Algorithm
Pipelined Floating-Point Unit
Improved Instruction Execution Time
Separate 16K Code and 16K Data Caches
Writeback MESI Protocol in the Data Cache
64-Bit Data Bus
Enhanced Bus Cycle Pipelining
Address Parity
Internal Parity Checking
Execution Tracing
Performance Monitoring
IEEE 1149.1 Boundary Scan
System Management Mode
Virtual Mode Extensions
0.25 Micron Process
Technology
SL Power Management Features
Pool of four write buffers used by both pipes
•
The architecture and internal features of the
mobile Pentium processor with MMX technology
on 0.25 micron
are identical to the desktop version
specifications provided in the
Pentium
®
Processor
Family Developer’ Manual
(Order Number
s
241428), except several features not used in
mobile applications which have been eliminated to
streamline it for mobile applications.
This document should be used in conjunction with
Pentium
®
Processor Family Developer’ Manual
s
(Order Number: 241428)
4
INTEL [ INTEL CORPORATION ]
