MOBILE PENTIUM
®
PROCESSOR WITH MMX™ TECHNOLOGY
buffers that can hold up to four successive code
streams.
2.2.4. Enhanced pipeline
An additional pipeline stage has been added and
the pipeline has been enhanced to improve
performance. The integration of the MMX
technology pipeline with the integer pipeline is very
similar to that of the floating-point pipeline. Under
some circumstances, two MMX instructions or one
integer and one MMX instruction can be paired and
issued in one clock cycle to increase throughput.
The enhanced pipeline is described in more detail
in the
Pentium® Processor Family Developer’
s
Manual
(Order Number 241428).
Deeper write buffers.
A pool of four write buffers
is now shared between the dual pipelines to
improve memory write performance.
micron
consumes significantly less power at even
higher speeds. The mobile Pentium processor with
MMX technology
on 0.25 micron
is the first Intel
microprocessor utilizing 0.25 micron technology.
3.0.
MOBILE PENTIUM
®
PROCESSOR WITH MMX™
TECHNOLOGY PINOUT
Mobile Differences from
Desktop
3.1.
To better streamline the part for mobile
applications, the following features have been
eliminated: Upgrade, Dual Processing (DP), and
Master/Checker functional redundancy.
Table 1 lists the corresponding pins which exist on
the desktop Pentium processor with MMX
technology but have been removed on
the mobile
Pentium processor with MMX technology on 0.25
micron.
2.3.
0.25 micron technology
The 0.25 micron technology is the latest state-of-
the-art CMOS manufacturing process Intel unveiled
on April 12, 1997, which enables the use of lower
core supply to sub-2V. As a result,
the mobile
Pentium processor with MMX technology on 0.25
Table 1. Signals Removed in Mobile Pentium
Signal
ADSC#
®
Processor with MMX™ Technology 200/233 MHz
Function
Additional Address Status. This signal is mainly used for large or standalone L2
cache memory subsystem support required for high-performance desktop or
server models.
Additional Burst Ready. This signal is mainly used for large or standalone L2
cache memory subsystem support required for high-performance desktop or
server models.
CPU Type. This signal is used for dual processing systems.
Dual/Primary processor identification. This signal is only used for an upgrade
processor.
Functional Redundancy Checking. This signal is only used for error detection via
processor redundancy and requires two Pentium
®
processors (master/checker).
Private Bus Grant. This signal is only used for dual processing systems.
Private Bus Request. This signal is used only for dual processing systems.
Private Hit. This signal is only used for dual processing systems.
Private Modified Hit. This signal is only used for dual processing systems.
BRDYC#
CPUTYP
D/P#
FRCMC#
PBGNT#
PBREQ#
PHIT#
PHITM#
8
INTEL [ INTEL CORPORATION ]
