®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY
this section is not the actual text which will be
marked on the packages).
3.2.
TCP Pinout and Pin
Descriptions
The text orientation on the top side view drawings in
this section represent the orientation of the ink mark
on the actual packages (Note that the text shown in
3.2.1.
MOBILE PENTIUM® PROCESSOR
WITH MMX™ TECHNOLOGY ON 0.25
MICRON TCP PINOUT
VCC2
VCC3
VSS
1
2
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
VCC2
VSS
A11
3
HOLD
WB/WT#
VCC2
VSS
A10
4
5
VCC3
VSS
A9
6
7
NA#
8
VSS
VCC2
A8
BOFF#
BRDY#
VCC2
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VCC3
VSS
A7
KEN#
AHOLD
INV
A6
VCC3
VCC2
VSS
A5
EWBE#
VCC2
VSS
VCC3
VSS
A4
VCC3
VSS
CACHE#
M/IO#
VCC3
VSS
A3
VSS
VCC2
VCC3
VSS
BP3
216
215
214
213
VSS
VCC2
BP2
A31
A30
PM1/BP1
PM0/BP0
FERR#
VSS
A29
212
211
210
209
208
207
206
205
204
203
202
201
200
199
A28
VCC3
VSS
VCC2
IERR#
VCC3
VSS
A27
A26
A25
A24
DP7
VCC3
VSS
D63
D62
A23
D61
A22
VCC2
VSS
A21
NMI
VCC3
VSS
R/S#
INTR
SMI#
VCC2
VSS
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
D60
D59
D58
D57
IGNNE#
INIT
VCC2
VSS
PEN#
VCC2
VSS
VCC3
VSS
D56
VCC2
VSS
DP6
D55
BF0
D54
BF1
VCC2
VSS
BF2
VCC2
VSS
VCC3
VSS
STPCLK#
VCC2
VSS
D53
D52
D51
VCC3
VCC2
VSS
D50
VCC2
VSS
NC
VCC3
VSS
VCC2
VSS
D49
VCC2
VSS
D48
DP5
VCC2
VSS
D47
VCC3
VSS
VCC2
TRST#
VSS
D46
D45
VCC2
TMS
D44
D43
TDI
VCC3
VSS
TDO
TCK
PP0116
Figure 2. TCP Mobile Pentium ® Processor with MMX™ Technology on 0.25 Micron Pinout
9
INTEL [ INTEL ]
