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80523TX233512 参数 Datasheet PDF下载

80523TX233512图片预览
型号: 80523TX233512
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 233MHz, BICMOS, MBGA240]
分类和应用: 信息通信管理外围集成电路
文件页数/大小: 67 页 / 718 K
品牌: INTEL [ INTEL ]
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®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY  
Table 13. Power Dissipation Requirements for Thermal Design  
Parameter  
Typical1  
Max2  
Unit  
Frequency  
Notes  
Thermal Design Power  
4.1  
5.0  
5.5  
7.6  
Watts  
Watts  
Watts  
Watts  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
Active Power5  
2.3  
2.7  
3.0  
4.5  
Watts  
Watts  
Watts  
Watts  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
Stop Grant / Auto Halt Powerdown  
Power Dissipation3  
0.42  
0.46  
0.53  
0.70  
Watts  
Watts  
Watts  
Watts  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
Stop Clock Power4  
0.02  
0.02  
0.02  
0.05  
0.05  
0.05  
0.06  
Watts  
Watts  
Watts  
Watts  
166 MHz  
200 MHz  
233 MHz  
266 MHz  
NOTES:  
1.  
This is the typical power dissipation in a system. This value is expected to be the average value that will be measured in  
a system using a typical device at VCC2 = 1.8V (166/200/233 MHz) or 2.0V (266 MHz) running typical applications. This  
value is highly dependent upon the specific system configuration. Typical power specifications are not tested.  
2.  
Systems must be designed to thermally dissipate the maximum thermal design power unless the system uses thermal  
feedback to limit processor’s maximum power. The maximum thermal design power is determined using a worst-case  
instruction mix with VCC2 = 1.8V (166/200/233 MHz) or 2.0V (266 MHz) and also takes into account the thermal time  
constant of the package.  
3.  
Stop Grant/Auto Halt Powerdown Power Dissipation is determined by asserting the STPCLK# pin or executing the HALT  
instruction. When in this mode, the processor has a new feature which allows it to power down additional circuitry to  
enable lower power dissipation. This is the power without snooping at Vcc2 = 1.8V/2.0V and with TR12 bit 21 set. In  
order to enable this feature, TR12 bit 21 must be set to 1 (the default is 0 or disabled). Stop grant/Auto Halt Powerdown  
power dissipation without TR12 bit21 set may be higher. The Max rating may be changed in future spec update.  
4.  
5.  
Stop Clock Power Dissipation is determined by asserting the STPCLK# pin and then removing the external CLK input.  
This is specified at a Tcase of 50 ºC.  
Active power is the average power measured in a system using a typical device running typical applications under  
normal operating conditions at nominal Vcc and room temperature.  
33  
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