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80523TX233512 参数 Datasheet PDF下载

80523TX233512图片预览
型号: 80523TX233512
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 233MHz, BICMOS, MBGA240]
分类和应用: 信息通信管理外围集成电路
文件页数/大小: 67 页 / 718 K
品牌: INTEL [ INTEL ]
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®
MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY  
4.3.3.  
CONNECTION SPECIFICATIONS  
Powerdown state, or transitioning from HALT to the  
Normal state. All of these examples may cause  
abrupt changes in the power being consumed by  
the processor.  
All NC pins must remain unconnected.  
For reliable operation, always connect unused  
inputs to an appropriate signal level. Unused active  
low inputs should be connected to VCC3. Unused  
active high inputs should be connected to ground.  
Note that the Auto HALT Powerdown feature is  
always enabled even when other power  
management features are not implemented.  
4.3.4.  
AC TIMINGS FOR A 66-MHZ BUS  
Bulk storage capacitors with a low ESR (Effective  
Series Resistance) in the 10 to 100 µf range are  
required to maintain a regulated supply voltage  
during the interval between the time the current  
load changes and the point that the regulated  
power supply output can react to the change in  
load. In order to reduce the ESR, it may be  
necessary to place several bulk storage capacitors  
in parallel.  
The AC specifications given in Table 15 consist of  
output delays, input setup requirements and input  
hold requirements for the mobile standard 66 MHz  
external bus. All AC specifications (with the  
exception of those for the TAP signals and APIC  
signals) are relative to the rising edge of the CLK  
input.  
All timings are referenced to VCC3/2 for both "0" and  
"1" logic levels unless otherwise specified. Within  
the sampling window, asynchronous inputs must be  
stable for correct operation.  
These capacitors should be placed near the  
processor on both VCC2 plane and VCC3 plane to  
ensure that the supply voltages stay within  
specified limits during changes in the supply current  
during operation.  
Each valid delay is specified for a 0 pF load. The  
system designer should use I/O buffer modeling to  
account for signal flight time delays. Do not select a  
bus fraction and clock speed which will cause the  
processor to exceed its internal maximum  
frequency.  
For more detailed information, please contact Intel  
or refer to the Mobile Pentium Processor with  
MMX™ Technology: Power Supply Design  
Considerations application note (Order Number  
243306).  
35  
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