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MOBILE PENTIUM PROCESSOR WITH MMX™ TECHNOLOGY
3.6.
Pin Reference Tables
Table 6. Output Pins1
Name
Active Level
Low
When Floated
Bus Hold, BOFF#
ADS#
APCHK#
BE7#-BE4#
BREQ
Low
Low
Bus Hold, BOFF#
Bus Hold, BOFF#
High
Low
CACHE#
FERR#
HIT#
Low
Low
HITM#2
HLDA
Low
High
Low
IERR#
LOCK#
Low
Bus Hold, BOFF#
Bus Hold, BOFF#
M/IO#, D/C#, W/R#
PCHK#
n/a
Low
BP3-2, PM1/BP1, PM0/BP0
PRDY
High
High
High
High
Low
PWT, PCD
Bus Hold, BOFF#
Bus Hold, BOFF#
SCYC
SMIACT#
TDO
n/a
All states except Shift-DR and Shift-IR
NOTE:
1.
2.
All output and input/output pins are floated during tristate test mode (except TDO).
HITM# pin has an internal pull-up resistor.
27
INTEL [ INTEL ]
