Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Figure 7. BCLK, PICCLK, and TCK Generic Clock Waveform
th
tr
V2
V3
CLK
V1
tf
tl
tp
Tr
Tf
Th
Tl
=
=
=
=
=
T5, T25, T34, (Rise Time)
T6, T26, T35, (Fall Time)
T3, T23, T32, (High Time)
T4, T24, T33, (Low Time)
Tp
T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK is referenced to 0.5V. TCK is referenced to V REF - 200mV.
PICCLK is referenced to 0.7V.
V2 = BCLK is referenced to 2.0V. TCK is referenced to VREF - 200mV.
PICCLK is referenced to 1.7V.
V3 = BCLK and PICCLK are referenced to 1.25V. TCK is referenced to V
.
REF
Figure 8. System Bus Valid Delay Timings
CLK
Tx
Tx
Valid
Valid
V
Signal
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group; 0.75V for CMOS, APIC and TAP signal groups
Figure 9. System Bus Setup and Hold Timings
CLK
Th
Ts
V
Valid
Signal
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
= 1.0V for AGTL+ signal group; 0.75V for APIC and TAP signal groups
V
Datasheet
31
INTEL [ INTEL ]
