Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
Table 13. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
Active and
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
BCLKs
8
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
8, 11
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after VCC
, VTT, VCC , and BCLK become stable.
CORE CMOS
Table 14. System Bus AC Specifications (Reset Conditions) 1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time
Before deassertion
of RESET#
4
BCLKs
10
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time
After clock that
deasserts RESET#
2
20
BCLKs
10
10
10
10
T18: Reset Configuration Signals (A20M#,
IGNNE#, LINT[1:0]) Setup Time
2
2
2
T19: Reset Configuration Signals (A20M#,
IGNNE#, LINT[1:0]) Delay Time
T20: Reset Configuration Signals (A20M#,
IGNNE#, LINT[1:0]) Hold Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. This parameter does not apply to the Pentium III processor. The Pentium III processor does not sample these
signals at RESET# to determine the multiplier ratio as some previous Intel processors have done. The
multiplier ratio is set during manufacturing for each processor and cannot be changed. The multiplier ratios
are defined in Table 11.
Table 15. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter
T21: PICCLK Frequency
Min
Max
Unit
Figure
Notes
2.0
30.0
10.5
10.5
0.25
0.25
5.0
33.3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
T22: PICCLK Period
500.0
7
7
T23: PICCLK High Time
@ > 1.7V
T24: PICCLK Low Time
7
@ < 0.7V
(0.7V - 1.7V)
(1.7V - 0.7V)
4
T25: PICCLK Rise Time
3.0
3.0
7
T26: PICCLK Fall Time
7
T27: PICD[1:0] Setup Time
T28: PICD[1:0] Hold Time
T29a: PICD[1:0] Valid Delay (Rising Edge)
T29b: PICD[1:0] Valid Delay (Falling Edge)
9
2.5
9
4
1.5
8.7
7, 8
7, 8
4, 5, 6
1.5
12.0
4, 5, 6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
Datasheet
29
INTEL [ INTEL ]
