Pentium® III Processor for the PGA370 Socket at 500 MHz to 866 MHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in Table 17, Table 18, and Table 23 ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK and PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 17 describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals. Figure 14 describes the signal quality
waveform for the system bus clock at the processor pins.
Table 17. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins 1
T# Parameter
V1: BCLK VIL
Min
Nom
Max
Unit
Figure
Notes
0.500
0.700
V
V
V
V
V
V
V
V
V
14
14
14
14
14
14
14
14
14
V1: PICCLK VIL
V2: BCLK VIH
2.000
2.000
–0.58
2.000
2.000
V2 PICCLK VIH
V3: VIN Absolute Voltage Range
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
V5: BCLK Falling Edge Ringback
V5: PICCLK Falling Edge Ringback
3.18
2
2
2
2
0.500
0.700
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Figure 14. BCLK, PICCLK Generic Clock Waveform at the Processor Pins
V3
V4
V2
V1
V5
V3
34
Datasheet
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