Signal Description
BIOS-specific bit SGME (bit 5 in CNF). This bit programs the hot plug controller to generate an
SCI message to MCH instead of an MSI or a pin interrupt to the internal I/OxAPIC. This SCI
message is ultimately routed by MCH to the ICH via the GPE# pin. On assertion of the GPE# pin
to the ICH, the ICH pulls the SCI pin to the processor, which in turn wakes up the ACPI handler.
All logic in the SHPC function is the same as for normal MSI or pin interrupts.
2.13.10 Error Handling
The standard hot-plug controller can detect a variety of error conditions (refer to the PCI Standard
Hot-Plug Controller and Subsystem Specification, Revision 1.0 for details) and it can be
programmed to either send an error message on the PCI Express interface or raise an interrupt.
2.13.11 Assumptions and Intel® 6702PXH 64-bit PCI Hub
Requirements
2.13.11.1 MRL Opening during the Sequence
While executing an enable or disable sequence, if the MRL of one of the cards is opened then the
Intel® 6702PXH 64-bit PCI Hub performs the auto power down for that slot after executing the
current enable/disable operation. As the maximum time required to enable is disable is 319 ms, the
maximum delay between MRL open and auto-power down would be less than 320 ms.
2.13.11.2 Power Fault
The power controller/slot control logic is responsible for removing power from the slot and
isolating the card in the event of a power fault. The Intel® 6702PXH 64-bit PCI Hub would notify
software in the event of a power fault and wait for the slot disable command from the software to
disable the appropriate slot.
2.14
Addressing
2.14.1
I/O Window Addressing
I/O accesses from the PCI Express bus always target the PCI bus. No I/O accesses are allowed
from PCI to PCI Express and nor are any I/O accesses to internal devices (APIC, CSR, SHPC)
allowed.
2.14.1.1
Mode I/O Access
One I/O window can be set up for forwarding I/O transactions from the PCI Express to the PCI bus.
No I/O transactions can be forwarded from the PCI to the PCI Express bus. The registers and
register bits listed below define the setup and control of this I/O window:
• I/O Base and Limit Address Registers
• I/O Enable bit in the Command Register
• Enable 1-Kbyte granularity in the Intel® 6702PXH 64-bit PCI Hub Configuration Register
Intel® 6702PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
