Electrical Characteristics
3. See the timing measurement conditions in Figure 4-5 and the PCI-X Electrical and Mechanical Addendum,
Revision 2.0a.
4. PAPCIRST# is asserted and deasserted asynchronously with respect to CLK.
5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control
signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first
PAFRAME# and must be floated no later than one clock before PAFRAME# is asserted.
8. Device must meet this specification independent of how many outputs switch simultaneously.
Table 4-19. PCI-X Mode 1 General Timing Parameters
PCI-X 133 MHz
Min Max
0.7
PCI-X 66 MHz
Min Max
0.7 3.1
Symbol
Parameter
Units
Notes
Tval
val(ptp)
CLK to Signal Valid Delay
(bused signals)
3.1
3.1
ns
1, 2, 3,
10, 11
T
CLK to Signal Valid Delay
(point-to-point signals)
0.7
0
0.7
0
3.1
ns
ns
1, 2, 3,
10, 11
Ton
Float to Active Delay
1, 7, 10,
11
Toff
Tsu
Active to Float Delay
7
7
ns
ns
1, 7, 11
3, 4, 8
Input Setup Time to CLK
(bused signals)
1.2
1.2
1.7
1.7
Tsu(ptp)
Input Setup Time to CLK
(point-to-point signals)
ns
3, 4
Th
Input Hold Time from CLK 0.5
0.5
1
ns
4
5
Trst
Reset Active Time after
Power Stable
1
ms
Trst-clk
Trst-off
Reset Active to CLK Stable 100
100
µs
5
Reset Active to Output
Float Delay
40
50
40
50
ns
5, 6
Trrsu
Trrh
Trhfa
Trhff
PAREQ64# to RSTIN#
Setup Time
10
0
10
0
ns
RSTIN# to PAREQ64#
Hold Time
ns
RSTIN# High to First
Configuration Access
227
5
227
5
clocks
clocks
ms
RSTIN# High to First
PAFRAME# Assertion
Tpvrh
Tprsu
Tprh
Power Valid to RSTIN#
High
100
100
10
0
PCI-X Initialization Pattern 10
to RSTIN# Setup Time
clocks
ns
RSTIN# to PCI-X
Initialization Patter Hold
Time
0
50
50
9
Trlcx
Delay from RSTIN# Low to
CLK Frequency Change
0
0
ns
172
Intel® 6702PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
