Electrical Characteristics
NOTES:
1. Refer to Figure 4-4. For timing and measurement condition details, refer to the PCI-X Addendum to the PCI
Local Bus Specification, Revision 2.0a.
2. Minimum times are measured at the package pin (not the test point).
3. Setup time for point-to-point signals applies to PAREQ_5:0]# and PAGNT_5:0]# only. All other signals are
bused.
4. See the timing measurement conditions in Figure 4-5.
5. RST# is asserted and deasserted asynchronously with respect to CLK.
6. All output drivers must be floated when RSTIN# is active.
7. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
9. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control
signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first
PAFRAME# and must be floated no later than one clock before PAFRAME# is asserted.
10.A PCI-X Mode 1 device is permitted to have the minimum values shown for Tval, Tval(ptp) and Ton only in
PCI-X mode. In conventional mode, the device must meet the requirements specified in the PCI Local Bus
Specification, Revision 2.3 for the appropriate clock frequency.
11.Device must meet this specification independent of how many outputs switch simultaneously.
Figure 4-6. PCI-X Mode 1 Output Timing
V_th
V_tl
CLK
V_test
T_val
OUTPUT
DELAY
V_tfall
T_val
V_trise
OUTPUT
DELAY
Tri-State
OUTPUT
T_on
T_off
Intel® 6702PXH 64-bit PCI Hub Datasheet
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