Electrical Characteristics
4.3.2
PCI and PCI-X Interface Timing
Table 4-18. Conventional PCI Interface Timing
Functional Operating Range (VCC33 = 3.3V + 5%, Tcase=0°C to 105°C)
66 MHz 33 MHz
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
Tval
CLK to Signal Valid Delay- bused signals
2
2
6
6
2
2
11
12
ns
ns
1, 2, 3
1, 2, 3
T
val(ptp) CLK to Signal Valid Delay-point-to-point
signals
Ton
Toff
Tsu
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK-Bused signals
2
2
ns
ns
1, 7
1, 7
3, 4, 8
3, 4
4
14
28
3
5
7
10,12
0
ns
T
su(ptp) Input Setup Time to CLK; point-to-point
ns
Th
Input Hold Time from CLK
0
ns
Trst
Reset Active Time
1
1
ms
5
Trst-clk
Trst-off
Trrsu
Trrh
Reset Active Time after CLK stable
Reset Active to output float delay
PAREQ64# to RSTIN# setup time
RSTIN# to PAREQ64# hold Time
RSTIN# high to first configuration access
100
100
µs
5
40
50
40
50
ns
5, 6
10
0
10
0
clocks
ns
9
Trhfa
Trhff
225
225
clocks
clocks
RSTIN# high to first PAFRAME#
Assertion
5
5
Tpvrh
Power Valid to RSTIN# High
100
100
ms
NOTES:
1. See Figure 4-4. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc
.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. PAREQ_[5:0]# and PAGNT_[5:0]# are point-to-point signals and have different input setup times than do
bused signals. PAGNT_[5:0]# and PAREQ_[5:0]# have a setup of 5 ns at 66 MHz. All other signals are
bused.
4. See Figure and the measurement conditions in the PCI-X Electrical and Mechanical Addendum, Revision
2.0a.
5. If PAM66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Specification,
Revision 2.3. RSTIN# is asserted and deasserted asynchronously with respect to CLK.
6. When PAM66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be reduced
to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when PAM66EN is deasserted.
7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time. Refer to the PCI Local Bus Specification, Revision 2.3 for more details.
9. Maximum value is also limited by delay to the first transaction (Trhff).
170
Intel® 6702PXH 64-bit PCI Hub Datasheet
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